(1) Field of the Invention
The present invention relates to integrated circuit memory devices on a semiconductor substrates, and more particularly to a method for fabricating a ultra high density Read-Only-Memory (ROM) device.
(2) Description of the Prior Art
Read-Only-Memory (ROM) circuits are used extensively in the electronics industry to permanently store information in electronic equipment, such as computers, microprocessor systems and the likes. The information, such as micro-instructions, is stored so that the information is available the instant that the equipment, containing the ROM circuit, is turned on.
Memory cells are fabricated on a portion of the ROM device consisting of an array of single transistor, typically field effect transistor (FET), arranged in rows and columns. The array of FETs are built by first forming an array of closely spaced parallel electrically conducting line regions in the substrate called "bit lines". The bit lines serve as the source/drain regions of the FETs, and also serve as the electrical interconnections to the peripheral circuits for outputting the stored binary data. The buried bit lines are usually formed in the substrate by ion implantation and a thermal oxide is then grown on the substrate forming the gate oxide of the FET between the bit lines. The thermal oxide also provides the electrical insulation layer over the bit lines. A plurality of closely spaced parallel conducting line, called "word lines," usually formed from a doped polysilicon layer, are then formed on the substrate having an orthogonal direction to the buried bit lines, for example alone the rows direction. The word lines serve as the gate electrode of the FETs and also function as the electrical interconnection to the peripheral address decode circuit. The array of ROM cells are then coded with information, such as micro-instruction, by permanently rendering selected transistors non-conducting during processing while non-coded cells can be switch on, when accessed by way of the address decode circuits. The coded information represented by a change or no change in the voltage level at the output circuit are used to represent the binary 1's and 0's.
The code for the ROM is introduced during semiconductor processing by using a ROM code mask during one of the processing steps. The presence or absence of the transistor can be achieved by designing the ROM code mask for patterning a diffusion, contacts or metal during ROM device processing. Typically, the patterning and thereby the coding is done at the substrate level, by ion implantation and an activation anneal, to achieve the highest layout density. The patterning at the contact and metal levels are used to achieve the fastest turn-around time to finished product.
For the conventional implantation method of coding, the select FETs receive a high implant dose, thereby increasing the threshold voltage V.sub.t, at which the FET turns-on, which is higher than the applied gate voltage V.sub.g that the FET will experience during operation. This makes them permanently non-conductive, and thereby coding the FET on the ROM array. The code implantation is done using a patterned photoresist mask having openings over the FET gate areas selected for coding. A ROM code implant, such as a boron (B.sup.11) implantation, is formed in the FET channel under the gate electrode. When the chip fabrication is complete, and the gate voltage V.sub.g is applied to the word line over the code implanted region via the address circuit, the high threshold FET in the coded cell does not turn on, and thereby, for example, can be used to represent a binary 0. However, in cell areas that are masked from the implantation, the low P.sup.- doped surface is inverted when a gate voltage V.sub.g is applied and the FET turns on. This provides an electrical conducting path between the source and drain formed from the buried bit lines and thereby can, for example, represents a binary 1.
Unfortunately, when the code implantation is performed the transverse straggle from the implant and the thermal cycle to activate the implanted atoms result in lateral diffusion of the dopant which causes counter-doping of the adjacent buried bit lines. This substantially constricts the width of the buried bit line adjacent to the code implant region and increases substantially the series resistance in the individual bit lines. The problem is further exacerbated if two adjacent memory cells are coded by ion implantation. Therefore, it is necessary to limit the design ground rule for the separation between adjacent bit lines in order to avoid this problem.
Another problem occurs because the ROM code implant mask is optically aligned to the polysilicon gate (word line) and not to the bit line, therefore, the indirect alignment requires additional relaxation of the design ground rules.
Still another problem occurs with the ROM code implantation technology. The code implantation necessary for the high V.sub.t must also provide excellent electrical isolation between adjacent buried bit lines. However, the highly doped implanted channel under the coded FET results in a lower junction breakdown voltage and more importantly to very high leakage currents between adjacent bit lines. The high leakage current result in very high standby currents, thereby substantially reducing the useful operating time of battery operated equipment, such as in lap top computers.
One method of improving the performance of read-only memory is described by T. D. H. Yiu, in U.S. Pat. No. 5,117,389 in which design changes form subarrays of memory cells that are selected by block select transistors and share a common metal bit line to reduce the bit line resistance. Although the circuit performance is improved, the semiconductor processing is substantially more complex and the increase in packing density of the ROM cells is not necessary improved.
Therefore, there is still a strong need in the semiconductor industry to minimize the resistance of the bit line, minimize the standby current while increasing the ROM cell density on the substrate without substantially increasing the process complexity.